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IS310 Exam 3 Chap 6 Vocab

  1. Address bus
  2. Buffer
  3. Buffer overflow
  4. Bus
  5. Bus arbitration unit
  6. Bus clock
  7. Bus cycle
  8. Bus master
  9. Bus protocol
  10. Bus slave
  11. Cache
  12. Cache controller
  13. Cache hit
  14. Cache miss
  15. Cache swap
  16. Channel
  17. Compression
  18. Compression algorithm
  19. Compression ratio
  20. Control bus
  21. Core
  22. Data bus
  23. Decompression algorithm
  24. Device controller
  25. Direct memory access (DMA)
  26. DMA controller
  27. External I/O buses
  28. Hit ratio
  29. Interrupt
  30. Interrupt code
  31. Interrupt handler
  32. Interrupt register
  33. I/O channel
  34. I/O port
  35. I/O wait states
  36. Law of diminishing returns
  37. Level one (L1) cache
  38. Level two (L2) cache
  39. Level three (L3) cache
  40. Linear address space
  41. Logical access
  42. Lossless compression
  43. Lossy compression
  44. Machine state
  45. Memory bus
  46. Moving Picture Experts Group (MPEG)
  47. MP3
  48. Multicore architecture
  49. Peer-to-peer bus
  50. Peripheral Component Interconnect (PCI)
  51. Peripheral devices
  52. Pop
  53. Push
  54. Scaling out
  55. Stack
  56. Stack overflow
  57. Stack pointer
  58. Storage bus
  59. Supervisior
  60. Video bus
Author
ttran1
ID
118263
Card Set
IS310 Exam 3 Chap 6 Vocab
Description
Vocab for chap 6
Updated

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