Neets Module 13 Assignment 3

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Neets Module 13 Assignment 3
2012-08-09 16:32:43

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  1. What will be the output of an X-OR gate when both inputs are HIGH?
    Low (0).
  2. A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?
    One or the other of the inputs must be HIGH, but not both at the same time.
  3. What will be the output of an X-NOR gate when both inputs are LOW?
  4. What advantage does a half adder have over a quarter adder?
    The half adder generates a carry.
  5. An X-OR gate may be used as what type of adder?
    Quarter adder.
  6. What will be the output of a half adder when both inputs are 1s?
    Sum equals 0 with a carry of 1.
  7. What type of adder is used to handle a carry from a previous circuit?
    Full adder.
  8. How many full adders are required to add four-digit numbers?
  9. What type of logic gates are added to a parallel adder to enable it to subtract?
    X-OR gates.
  10. How many of these gates would be needed to add a four-digit number?
  11. What are R-S FFs used for?
    Storing information.
  12. How many R-S FFs are required to store the number 100101 (Base 2)?
  13. For an R-S FF to change output conditions, the inputs must be in what states?
    1 and 0, or opposite states.
  14. How may R-S FFs be constructed?
    By cross-coupling NAND or OR gates.
  15. How many inputs does a T FF have?
  16. What is the purpose of using T FFs?
    To divide the input by 2.
  17. What are the inputs to a D FF?
    Clock and data.
  18. How long is data delayed by a D FF?
    Up to one clock pulse.
  19. What condition must occur to have a change in the output of a D FF?
    A positive-going clock pulse.
  20. What type of FF can be used as an R-S, a T, or a D FF?
    J-K flip-flop.
  21. What two inputs to a J-K FF will override the other inputs?
    Clear (CLR) and preset (PS or PR).
  22. How is the J-K FF affected if PS and CLR are both LOW?
    The flip-flop is jammed.
  23. What is a clock with regard to digital equipment?
    A timing signal.
  24. What is the simplest type of clock circuit?
    An astable or free-running multivibrator.
  25. What is needed to use a monostable or one-shot multivibrator for a clock circuit?
  26. What type of clock is used when more than one operation is to be completed during one clock cycle?
    A multiphase clock.
  27. What is the modulus of a five-stage binary counter?
  28. An asynchronous counter is also called a ___________ counter.
  29. J-K FFs used in counters are wired to perform what function?
  30. What type of counter has clock pulses applied to all FFs?
  31. What is the largest count that can be indicated by a four-stage counter?
    1111 or 15
  32. How many stages are required for a decade counter?
  33. How many stages are required to store a 16-bit word?
  34. Simultaneous transfer of data may be accomplished with what type of register?
  35. How are erroneous transfers of data prevented?
    By clearing the register.
  36. Serial-to-parallel and parallel-to-serial conversions are accomplished by what type of circuit?
    Shift register.
  37. What type of data transfer requires the most time?
  38. What is the main disadvantage of parallel transfer?
    Requires more circuitry.
  39. How many FFs would be required for an 8-bit shift register?
  40. How many clock pulses are required to output a 4-bit number in serial form?
  41. What are RTL, DTL, and TTL examples of?
    Logic families.
  42. What type of logic family uses diodes in the input?
    DTL (diode transistor logic).
  43. What is the most common type of integrated circuit packaging found in military equipment?
    DIPs (dual inline packages).
  44. Circuits that can be interconnected without additional circuitry are known as ____________ circuits.