ECET 100 Summary: Week 5

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Author:
ktess06
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200178
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ECET 100 Summary: Week 5
Updated:
2013-02-12 21:52:13
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Logic Gates
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  1. The inverter output is the complement of the input.
  2. The AND gate output is HIGH only when all the inputs are High.
  3. The OR gate output is HIGH when any of the inputs is HIGH.
  4. The NAND gate output is LOW only when all the inputs are HIGH.
  5. The NAND can be viewed as a negative-OR whose output is HIGH when any input is LOW
  6. The NOR gate output is LOW when any of the inputs is HIGH.
  7. The NOR can be viewed as a negative-AND whose output is HIGH only when all the inputs are LOW.
  8. The exclusive-OR gate output is HIGH when the inputs are not the same.
  9. The exclusive-NOR gate output is LOW when the inputs are not the same.
  10. An array of AND gates consisting of a matrix of programmable interconnections.
    AND array
  11. A logic gate that produces a HIGH output only when all the inputs are HIGH.
    AND gate
  12. The mathematics of logic circuits.
    Boolean algebra 
  13. The inverse or opposite of a number. LOW is the complement of HIGH, and 0 is the complement of 1.
    Complement
  14. To activate or put into an operational mode; an input on a logic circuit that enables its operation.
    Enable
  15. A logic gate that produces a HIGH output only when its two inputs are at opposite levels.
    Exclusive-OR (XOR) gate
  16. A logic gate that produces a LOW only whebn the two inputs are at opposite levels.
    Exclusive-NOR gate
  17. The number of equivalent gate inputs of the same family series that a logic gate can drive.
    Fan-out
  18. A logic circuit that inverts or complements its input.
    Inverter
  19. A logic gate that produces a LOW output only when all the inputs are HIGH.
    NAND gate
  20. A logic gate in which the ouput is LOW when one or more of the inputs are HIGH.
    NOR gate
  21. A logic gate that produces a HIGH output when one or more inputs are HIGH.
    OR gate
  22. The time interval between the occurrence of an input transition and the occurrence of the corresponding output transition in a logic circuit.
    Propagation delay time
  23. A diagram of waveforms showing the proper timing relationship of all the waveforms.
    Timing diagrams
  24. A table showing the inputs and corresponding output(s) of a logic circuit.
    Truth table 
  25. A measure of fan-out. One gate input represents one unit load to the output of a gate within the same IC family
    Unit load

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