Comp org test 2

Card Set Information

Author:
cjcStudygroup
ID:
216482
Filename:
Comp org test 2
Updated:
2013-04-29 03:48:52
Tags:
Comp org final
Folders:

Description:
Review test questions.
Show Answers:

Home > Flashcards > Print Preview

The flashcards below were created by user cjcStudygroup on FreezingBlue Flashcards. What would you like to do?


  1. Consider the details of MARIE's StoreI command, given in RTN:

    MAR <- X
    MBR <- M[MAR]
    MAR <- MBR
    MBR <- AC
    M[MAR] <- MBR

    Describe the signal pattern necessary to implement MARIE's StoreI command.
    • MAR <- X |  T0 P0P1P2 P3
    • MBR <- M[MAR] | T1 P3P4
    • MAR <- MBR  | T2 P0P1 P3
    • MBR <- AC   |  T3 P2 P3P4
    • M[MAR] <- MBR |  T4 P0P1
    • [Reset Counter] |  T5Cr
  2. A digital computer has a memory unit with 32 bits per word. The instruction set consists of 216 different operations. All instructions have an operation code part (opcode) and an address part (allowing for only one address). Each instruction is stored in a word of memory.

    a)How many bits are needed for the opcode?

    b)How many bits are left for the address part of the instruction?

    c)What is the maximum allowable size for memory?

    d)What is the largest unsigned binary number that can be accommodated in one word of memory?
    a) 216 opcodes implies we need 28 = 8 bits (which will handle 256 opcodes totally)

    b) 32-8=24 bits

    c) Since we have 24 bits in the address portion of the instruction, we can address 224 words.

    d) 232 - 1
  3. Suppose that 128 x 8 RAM chips are used to provide a memory capacity 4096 bytes?(Hint: 128=27 , 4096=212 )

    a) How many address lines (i.e., bits in the address) are needed for 4096 bytes?

    b) How many address lines (i.e., bits in the address) must go to each chip?

    c) How many RAM chips are needed?

    d) How many address lines (i.e., bits in the address) are needed for each RAM chip(i.e., how many bits of the address must be used to determine the RAM chip)?

    e) If high-order interleaving is used, where would address ABC16 (ABC16=1010101111002)be located (i.e, which chip # will the address be located on)?

    f) If low-order interleaving is used, where would address ABC16 (ABC16=1010101111002)be located (i.e, which chip # will the address be located on)?
    a) 12 (4096=212)

    b) 7 (128=27)

    • c) 27x = 212
    •        x =212/27
    •           = 25
    •           = 32

    d) 5 (32=25)

    e) Chip 101012 = Chip 2110

    f) Chip 111002 = Chip 2810
  4. Explain why, in MARIE, the PC is only 12 bits wide and the MBR is 16 bits wide.
    MARIE can handle 16-bit data, so the MBR must be 16 bits wide. However, MARIE's memory is limited to 4096 address locations, so the PC only needs to be 12 bits wide to hold the largest address.
  5. Consider the following MARIE program:

    Address || Program  || Hex Code
                     Org 100                
      100     ||  Load D   ||  110E   
      101     ||  Subt C   ||  410D    
      102     ||  Store D  ||  210E    
      103     ||  Add A    ||  310B    
      104     ||  Store A  ||  210B    
      105     ||  JumpI A  || C10B    
      106     ||  AddI B    || B10C    
      107     ||  Subt C    || 410D    
      108     ||  Store B   || 210C    
      109     ||  Jump X   || 910A    
      10A     || X, Halt     || 7000    
      10B     || A, Hex 99 || 0099    
      10C     || B, Hex 10F|| 010F    
      10D     || C, Hex 1   || 0001    
      10E     || D, Hex 68  || 0068   
      10F     || E, Hex 3    || 0003   

    a) List the hexadecimal code for each instruction.

    b) Draw the symbol table.
    a) See Above.

    • b)
    •       Symbol   ||   Location
    •             X      ||    10A
    •             A      ||    10B
    •             B      ||    10C
    •             C      ||    10D
    •             D      ||    10E
    •             E      ||    10F
  6. Explain the steps in the fetch-decode-execute cycle. Your explanation must include what is happening in the various registers.
    • Fetch: Load the PC into the MAR; fetch the instruction and place it into the IR; increment PC by 1;
    • Decode: Decode the instruction using IR[15-12]; if necessary, place IR[11-0] into MAR and fetch operand, placing result into MBR;
    • Execute: Execute instruction
  7. Consider the following expression, given in in x notation: 

    X = A - B + C (D * E - F)/(G + H * K)

    a)Write the expression in post x (reverse Polish notation). Remember the rulesof precedence for arithmetic operations.

    b) Write a program to evaluate the arithmetic statement using a stack organized computer with zero-address instructions (so only push and pop can access memory).
    a) X = A B-CDE*F-GHK*+/*+

    • b)
    • PUSH A
    • PUSH B
    • SUBT
    • PUSH C
    • PUSH D
    • PUSH E
    • MULT
    • PUSH F
    • SUBT
    • PUSH G
    • PUSH H
    • PUSH K
    • MULT
    • ADD
    • DIV
    • MULT
    • ADD
    • POP X
  8. Show how AB01CD2316 would be stored by machines with 32-bit words, using little endian and big endian format. Assume each value starts at address 2016. Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory locations.
    • Address ->  || 2016 || 2016  || 2016 || 2016
    • Big Endian   ||  AB   ||   01   ||  CD   || 23
    • Little Endian ||  23   ||   CD  ||   01   || AB

What would you like to do?

Home > Flashcards > Print Preview