CH-1 Motherboards Processors and Memory.txt

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CH-1 Motherboards Processors and Memory.txt
2014-04-10 05:14:56
Aplus Motherboards Memory Processors Computers
Chapter 1 Study guide
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  1. The __ motherboard has the processor and memory slots at right angles to the expansion cards. This arrangement puts the processor and memory in line with the fan output of the power supply, allowing the processor to run cooler. Standard __ motherboards measure 12" x 9.6" (305 x 244 mm).
    Advanced Technology Extended (ATX)
  2. One form factor that is designed to work in standard ATX cases, as well as its own smaller cases, is known as__. __ follows the ATX principle of component placement for enhanced cooling over pre-ATX designs but with a smaller footprint. With this smaller form come some trade-offs. For the compact use of space, you must give up quantity: quantity of memory slots, motherboard headers, expansion slots, integrated components. Fewer __ chassis bays designed with power supplies of lower wattage ATX motherboards but are shallower and square, measuring 9.6" x 9.6" (244 n 244 mm).
    Micro ATX
  3. The __ line of motherboard form factors was developed by VIA as a low-power, small form factor (SFF) board for specialty uses, such as home-theater systems and as embedded components. __ itself is not an actual form factor but a family of form factors. The family consists of the following form factors:Mini-ITX—6.7" x 6.7" (170 x170 mm)
    Nano-ITX—4.7" x 4.7" (120 x 120 mm)
    Pico-ITX—3.9"x 2.8" (100 x 72 mm)
    Mobile-ITX—2.4" x 2.4" (60 x 60 mm)
  4. Parallel computer-system components work on the basis of a __. A __, in this sense, is a common collection of signal pathways over which related devices communicate within the computer system. Expansion __ of various architectures, incorporate slots at certain points in the bus to allow insertion of external devices, or adapters, into the __, usually with no regard to which adapters are inserted into which slots; insertion is generally arbitrary. Other types of __s exist within the system to allow communication between the CPU and components with which data must be exchanged. The term __ is also used in any parallel or bit-serial wiring implementation where multiple devices can be attached at the same time in parallel or in series (daisy-chained).
    Bus Architecture
  5. A __ is a collection of chips or circuits that perform interface and peripheral functions for the processor. This collection of chips is usually the circuitry that provides interfaces for memory, expansion cards, and onboard peripherals and generally dictates how a motherboard will communicate with the installed peripherals. __ can be made up of one or several integrated circuit chips. Intel-based motherboards, for example, typically use two chips. The functions of __ can be divided into two major functional groups, called Northbridge and Southbridge.
  6. The __ subset of a motherboard’s chipset is the set of circuitry or chips that performs one very important function: management of high-speed peripheral communications. The __ is responsible primarily for communications with integrated video using AGP and PCIe and process or to-memory communications. Therefore, it can be said that much of the true performance of a PC relies on the specifications of the __ component and its communications capability with the peripherals it controls. When we use the term __, we are referring to a functional subset of a motherboard’s chipset. The __ is directly connected to the Southbridge. It controls the Southbridge and helps to manage the communications between the Southbridge and the rest of the computer.
  7. The communications between the CPU and memory occur over what is known as the __, which is just a set of signal pathways connecting the CPU and main memory, for instance. The clock signal that drives the __ is used to drive communications by certain other devices, such as AGP and PCIe slots, making them local-bus technologies.
    Front Side Bus FSB
  8. The __ if present, is a set of signal pathways between the CPU and Level 2 or 3 (external) cache memory. The __ uses the same clock signal that drives the FSB. If no backside bus exists, cache is placed on the frontside bus with the CPU and main memory.
    Backside Bus BSB
  9. The __ subset of the chipset is responsible for providing support to the onboard slower peripherals (PS/2, parallel ports, serial ports, Serial and Parallel ATA, and so on), managing their communications with the rest of the computer and the resources given to them. These components do not need to keep up with the external clock of the CPU and do not represent a bottleneck in the overall performance of the system. Any component that would impose such a restriction on the system should eventually be developed for FSB attachment.
  10. __ buses operate at 33 or 66MHz over a 32-bit (4byte) channel, resulting in data rates of 133 and 266MBps, respectively, with 133MBps being the most common, server architectures excluded. __ is a shared-bus topology, however, so mixing33 and 66MHz adapters in a 66MHz system will slow all adapters to 33MHz. Older servers might have featured 64-bit __ slots as well, which double the 32-bit data rates. __ slots and adapters are manufactured in 3.3 and 5V versions. Universal adapters are keyed to fit in slots based on either of the two voltages.
    PCI expansion
  11. Visually indistinguishable from 64-bit PCI, because it uses the same slots, __ takes the 66MHz maximum frequency of PCI to new heights, to the most common, 133MHz, and the current maximum, 533MHz. With an 8-byte (64-bit) bus, this translates to maximum throughput of 4266MBps, roughly 4.3GBps. Additionally, __ supports a 266MHz bus as well as the only frequency it shares with PCI, 66MHz, making __ slots compatible with PCI adapters. __ is targeted at server platforms with its speed and support for hot-plugging but is still no match for the speeds available with PCIe, which all but obviates __ today. __ also suffers from the same shared-bus topology as PCI, resulting in all adapters falling back to the frequency of the slowest inserted adapter.
    PCI-X Expansion Slots
  12. __ slots are known mostly for legacy video card use and have been supplanted in new installations by PCI Express slots and their adapters.__ slots were designed to be a direct connection between the video circuitry and the PC’s memory. They are also easily recognizable because they are usually brown and are located right next to the PCI slots on the motherboard. __ slots are slightly shorter than PCI slots and are pushed back from the rear of the motherboard in comparison with the position of the PCI slots. __ performance is based on the original specification, known as __ 1x. It uses a 32-bit (4-byte) channel and a 66MHz clock, resulting in a data rate of 266MBps. AGP 2x, 4x, and 8xspecifications multiply the 66MHz clock they receive to increase throughput linearly. For instance, __ 8xuses the66MHz clock to produce an effective clock frequency of 533MHz, resulting in throughput of 2133MBps over the 4-byte channel.
    AGP Expansion Slots
  13. __ has the advantage of being faster than AGP while maintaining the flexibility of PCI. __ has no plug compatibility with either AGP or PCI. __ motherboards still tend to have regular PCI slots for backward compatibility, but AGP slots typically are not also included. __ uses a switching component with point-to-point connections to slots, giving each component full use of the corresponding bandwidth and producing more of a startopology versus a bus.__ is a serial technology, striping datapackets across multiple serial paths to achieve higher data rates. __ uses the concept of lanes, which are the switched point-to point signal paths between any two __ components. Each lane that the switch interconnects between any two intercommunicating devices comprises a separate pair of wires for both directions of traffic. Each __ pairing between cards requires a negotiation for the highest mutually supported number of lanes. The single lane or combined collection of lanes that the switch interconnects between devices is referred to as a link. There are seven different link widths supported by __, designated x1, x2, x4, x8, x12, x16, and x32, There are three major versions of __ currently specified: 1.x, 2.x, and 3.0.
    PCIe Expansion Slots
  14. __ is defined in the PCIe specification as the ability to use a higher-capability slot for a lesser adapter. In other words, you can use a shorter (fewer-lane) card in a longer slot. For example, you can insert a x8 card into a x16 slot. The x8 card won’t completely fill the slot, but it will work at x8 speeds if __ is supported by the motherboard. Otherwise, the specification requires __ devices to operate at only the x1 rate. This is something to be aware of and investigate in advance.
  15. __ is possible only on open-ended slots although not specifically allowed in the official specification. Even if you find or make (by cutting a groove in the end) an open-ended slot that accepts a longer card edge, the inserted adapter cannot operate faster than the slot’s maximum rated capability because the required physical wiring to the PCIe switch in the Northbridge is not present.
  16. __ is a slot that can be found on some older Intel motherboards was a replacement for Intel’s even earlier Audio Modem Riser (AMR) slot, each of which appeared in quantities of no more than one per motherboard.The cards made for the __ slot contained circuitry for sound and analog modem as well as networking.
    Communications and Networking Riser CNR
  17. __ slots are the next most notable slots on a motherboard. These slots are for the modules that hold memory chips that make up primary memory that is used to store currently used data and instructions for the CPU.
  18. __ is one type of circuit board. __s differ in the number of conductors, or pins, that each particular physical form factor uses. Some common examples include 168-, 184-, and 240-pin configurations.
    dual inline memory module (DIMM)
  19. __ is an older memory form factor that began the trend of placing memory chips on modules. Different memory module form factors 30-pin __ (3.5" x .75") 72-pin __ (4.25" x 1") 168-pin DIMM (5.375" x 1?) 144-pin SODIMM (2.625" x 1") 72-pin SODIMM (2.375" x 1")
    Single inline memory module (SIMM)
  20. Sometimes the amount of primary memory installed is inadequate to service additional requests for memory resources from newly launched applications. One solution for this is to use the hard drive as additional RAM. This space on the hard drive is known as a swap file or a paging file. The swap file, pagefile.sys in modern Microsoft operating systems, is an optimized space that can deliver information to RAM at the request of the memory controller faster than if it came from the general storage pool of the drive.
    virtual memory
  21. __ is a very fast form of memory forged from static RAM. Cache improves system performance by predicting what the CPU will ask for next and prefetching this information before being asked. This paradigm allows the cache to be smaller in size than the RAM itself. Only the most recently used data and code or that which is expected to be used next is stored in cache. Cache on the motherboard is known as external cache because it is external to the processor; it’s also referred to as Level 2 cache (L2 cache).
  22. __ is internal cache because it is built into the processor’s silicon wafer, or die. The word core is often interchangeable with the word die. It is now common for chip makers to use extra space in the processor’s packaging to bring the L2 cache from the motherboard closer to the CPU. When L2 cache is present in the processor’s packaging, but not on-die, the cache on the motherboard is referred to as Level 3 cache (L3 cache). Unfortunately, due to the defacto naming of cache levels, the term L2 cache alone is not a definitive description of where the cache is located. The terms L1 cache and L3 cache do not vary in their meaning, however. The typical increasing order of capacity and distance from the processor die is L1 cache, L2 cache, L3 cache, RAM, HDD/SSD. This is also the typical decreasing order of speed. The following list includes representative capacities of these memory types.
    L1 cache—64KB (32KB each for data and instructions)
    L2 cache—256KB
    L3 cache—4MB–12MB RAM—4–16GB
    Level 1 cache
  23. The “brain” of any computer is the __.
  24. __ attached to it a CPU are used to draw away and disperse the heat a processor generates. This is done because heat is the enemy of micro-electronics.
    heat sink
  25. Modern CPU sockets have a mechanism in place that reduces the need to apply the considerable force to the CPU. __ sockets use a plastic or metal lever on one of the two lateral edges to lock or release the mechanism that secures the CPU’s pins in the socket. The CPU rides on the mobile top portion of the socket, and the socket’s contacts that mate with the CPU’s pins are in the fixed bottom portion of the socket.
    zero insertion force (ZIF)
  26. __is the name given to any software that is encoded in hardware, usually a read-only memory (ROM) chip, and can be run without extra instructions from the operating system. Most computers and large printers use firmware in some sense. The best example of firmware is a computer’s Basic Input/Output System (BIOS) routine, which is burned in to a chip. Also, some expansion cards, such as SCSI cards and graphics adapters, use their own firmware utilities for setting up peripherals.
  27. A memory chip contains the __ system software that boots the system and allows the operating system to interact with certain hardware in the computer. There is often a utility that gives you access to such bits of information as current live readings of the temperature of the CPU and the ambient temperature of the interior of the system unit. In such a page, you can set the temperature at which the __ sounds a warning tone and the temperature at which the __ shuts the system down to protect it. You can also monitor the instantaneous fan speeds, bus speeds, and voltage levels of the CPU and other vital landmarks to make sure they are all within acceptable ranges. You might also be able to set a lower fan-speed threshold at which the system warns you.
  28. A major function of the BIOS is to perform a process known as a__. __ is a series of system checks performed by the system BIOS and other high-end components, such as the SCSI BIOS and the video BIOS. Among other things, the __ routine verifies the integrity of the BIOS itself. It also verifies and confirms the size of primary memory. During __, the BIOS also analyzes and catalogs other forms of hardware, such as buses and boot devices, as well as manages the passing of control to the specialized BIOS routines mentioned earlier. The BIOS is responsible for offering the user a key sequence to enter the configuration routine as __ is beginning. Finally, once __ has completed successfully, the BIOS selects the boot device highest in the configured boot order and executes the master boot record (MBR) or similar construct on that device so that the MBR can call its associated operating system’s boot loader and continue booting up.
    power-on self-test (POST)
  29. Your PC has to keep certain settings when it’s turned off and its power cord is unplugged, these settings are kept in a special memory chip called the __. Actually,__ is a manufacturing technology for integrated circuits. The BIOS starts with its own default information and then reads information from the __, such as which hard drive types are configured for this computer to use, which drive(s) it should search for boot sectors, and so on. Any over lapping information read from the __ overrides the default information from the BIOS. A lack of corresponding information in the __ does not delete information that the BIOS knows natively. This process is a merge, not a write-over. __ memory is usually not upgradable in terms of its capacity and might be integrated into the BIOS chip or the Southbridge.
    Complementary metal oxide semiconductor CMOS and CMOS Battery
  30. __ and __ are used to configure various hardware options on the motherboard. Some legacy motherboards supported processors that use different core (internal) and I/O (external) voltages. Before this voltage regulation was automated, you had to set the motherboard to provide the correct voltage for the processor it was using. You did so by changing a setting on the motherboard with either a __ or a __. Many of the motherboard settings that were set using __ and __ switches are now either automatically detected or set manually in the BIOS setup program. Additionally, be careful not to place jumper caps (shunts) over pins just because they look like jumpers; they might be connector headers, the shorting of which could lead to wide spread circuit or component destruction.
    Jumpers and DIP Switches (dual inline package.)
  31. __ is a form of simultaneous multithreading (SMT). SMT takes advantage of a modern superscalar architecture. Superscalar processors are able to have multiple instructions operating on separate data in parallel. HTT-capable processors appear to the operating system to be two processors. As a result, the operating system can schedule two processes at the same time, as in the case of symmetric multiprocessing (SMP), where two or more processors use the same system resources. In fact, the operating system must support SMP in order to take advantage of __. If the current process stalls because of missing data caused by, say, cache or branch prediction issues, the execution resources of the processor can be reallocated for a different process that is ready to go, reducing processor downtime.
    Hyperthreading HTT
  32. A processor that exhibits a __ architecture has multiple completely separate processor dies in the same package. The operating system and applications see multiple processors in the same way that they see multiple processors in separate sockets. As with HTT, the operating system must support SMP to benefit from the separate processors. In addition, SMP is not a benefit if the applications run on the SMP system are not written for parallel processing. Dual-core and quad-core processors are common specific examples of the __ technology.
  33. CPU __ allows reducing the operating frequency of the CPU during times of less demand or during battery operation. CPU __ is very common in processors for mobile devices, where heat generation and system-battery drain are key issues of full power usage. You might discover __ in action when you use a utility that reports a lower CPU clock frequency than expected. If the load on the system does not require full-throttle operation, there is no need to push such a limit.
  34. The __ of the processor is generally described in clock frequency (MHz or GHz).
  35. Motherboards have always included oscillators, quartz crystals shaved down to a specific geometry so that engineers know exactly how they will react when a current is run through them. The phenomenon of a quartz crystal vibrating when exposed to a current is known as the __. The crystal (XTL) known as the system clock keeps the time for the flow of data on the motherboard. How the clock is used by the frontside bus leads to an effective clock rate known as the FSB speed.
    Piezoelectric Effect
  36. Many of today’s CPUs support __ in hardware, which eases the burden on the system that software-based __ imposes. In some cases, you must also first enable the __ support in the BIOS before it can be used. Motherboards have memory limits; operating systems have memory limits; CPUs have memory limits.
  37. __ is a rudimentary error-checking scheme that offers no error correction. Parity checking works most often on a byte, or 8bits, of data. A ninth bit is added at the transmitting end and removed at the receiving end so that it does not affect the actual data transmitted. The four most common __ schemes affecting this extra bit are known as even, odd, mark, and space. Even and odd __ are used in systems that actually compute parity. Mark (a term for a 1 bit) and space (a term for a 0 bit) parity are used in systems that do not compute parity but expect to see a fixed bit value stored in the parity location. Systems that do not support or reserve the location required for the parity bit are said to implement non-parity memory.
    Parity Checking
  38. The most basic model for implementing memory in a computer system uses eight memory chips to form a set. Each memory chip holds millions or billions of bits of information, each in its own cell. For every byte in memory, one bit is stored in each of the eight chips. A ninth chip is added to the set to support the parity bit in systems that require it. One or more of these sets, implemented as individual chips or as chips mounted on a memory module, form memory bank. A __ is required for the computer system to electrically recognize that the minimum number of memory components or the proper number of additional memory components has been installed. The width of the system data bus, the external bus of the processor, dictates how many memory chips or modules are required to satisfy a __.
    Memory Banks
  39. __ schemes operate on each byte in the set of memory chips. In each case, the number of bits set to a value of 1 is counted up. If there are an even number of 1 bits in the byte (0, 2, 4, 6, or 8), __ stores a 0 in the ninth bit, the parity bit; otherwise, it stores a 1 to even up the count.
    Even parity schemes
  40. __stores a 1 in the parity bit to make an even number of 1s odd and a 0 to keep an odd number of 1s odd. You can see that this is effective only for determining if there was a blatant error in the set of bits received, but there is no indication as to where the error is and how to fix it. Furthermore, the total 1-bit count is not important, only whether it’s even or odd.
    Odd parity
  41. __ are used in systems that want to see nine bits for every byte transmitted but don’t compute the parity bit’s value based on the bits in the byte. __ always uses a 1 in the parity bit
    Mark parity
  42. __ are used in systems that want to see nine bits for every byte transmitted but don’t compute the parity bit’s value based on the bits in the byte. __ always uses a 0.
    Space Parity
  43. The next step in the evolution of memory error detection is known as __. If memory supports __, check bits are generated and stored with the data. An algorithm is performed on the data and its check bits whenever the memory is accessed. If the result of the algorithm is all zeros, then the data is deemed valid and processing continues. __ can detect single-and double-bit errors and actually correct single-bit errors.
    Error Checking and Correction ECC
  44. Commonly speaking, the terms single-sided memory and double-sided memory refer to how some memory modules have chips on one side while others have chips on both sides. Double-sided memory is essentially treated by the system as two separate memory modules.
    Single-and Double-Sided Memory
  45. Standard memory controllers manage access to memory in chunks of the same size as the system bus’s data width. This is considered communicating over a single channel. Memory controllers that support dual-and triple-channel memory implementation were developed in an effort to alleviate the bottleneck between the CPU and RAM. Dual-channel memory is the memory controller’s coordination of two memory banks to work as a synchronized set during communication with the CPU, doubling the specified system bus width from the memory’s perspective. Triple-channel memory, then, demands the coordination of three memory modules at a time. The major difference between dual-and triple-channel architectures is that triple-channel memory employs a form of interleaving that reduces the amount of information transferred by each module.
    Single-, Dual-, and Triple-Channel Memory
  46. When you expand the memory in a computer, you are adding __ chips. You use __ to expand the memory in the computer because it’s a cheaper type of memory. __ chips are cheaper to manufacture than most other types because they are less complex. Dynamic refers to constant update signal. Currently, the most popular implementations of __ are based on synchronous DRAM and include SDRAM, DDR, DDR2, DDR3, and DRDRAM.
    dynamic random access memory DRAM
  47. __ is characterized by its independence from the CPUs external clock. __chips have codes on them that end in a numerical value that is related to the access time of the memory. Access time is essentially the difference between the time when the information is requested from memory and the time when the data is returned. Common access times attributed to __ were in the 40- to 120-nanosecond (ns) vicinity. A lower access time is obviously better for overall performance. Because __ is not synchronized to the frontside bus, you would often have to insert wait states through the BIOS setup for a faster CPU to be able to use the same memory as a slower CPU. These wait states represented intervals that the CPU had to mark time and do nothing while waiting for the memory subsystem to become ready again for subsequent access. Common __ technologies included Fast Page Mode (FPM), Extended Data Out (EDO), and Burst EDO (BEDO).
    Asynchronous DRAM
  48. __ shares a common clock signal with the computer's system-bus clock, which provides the common signal that all local-bus components use for each step that they perform. This characteristic ties __ to the speed of the FSB and hence the processor, eliminating the need to configure the CPU to wait for the memory to catch up.
    Synchronous DRAM
  49. __, every time the system clock ticks, 1 bit of data can be transmitted per data pin, limiting the bit rate per pin of __ to the corresponding numerical value of the clock's frequency. With todays processors interfacing with memory using a parallel data-bus width of 8 bytes (hence the term 64-bit processor ), a 100MHz clock signal produces 800MBps. Such memory modules are referred to as PC100, named for the true FSB clock rate they rely on. PC100 was preceded by PC66 and succeeded by PC133, which used a 133MHz clock to produce 1066MBps of throughput. Note that throughput in megabytes per second is easily computed as eight times the rating in the name. This trick works for the more advanced forms of __ as well. The common thread is the 8-byte system data bus. Incidentally, you can double throughput results when implementing dual-channel memory.
    Single Data Rate SDR SDRAM
  50. __ earns its name by doubling the transfer rate of ordinary SDRAM; it does so by double-pumping the data, which means transferring a bit per pin on both the rising and falling edges of the clock signal. This obtains twice the transfer rate at the same FSB clock frequency. It's the increasing clock frequency that generates heating issues with newer components, so keeping the clock the same is an advantage. The same 100MHz clock gives a __ SDRAM system the impression of a 200MHz clock in comparison to an SDR SDRAM system. For marketing purposes and to aid in the comparison of disparate products (__ vs. SDR, for example), the industry has settled on the practice of using this effective clock rate as the speed of the FSB.
    Double data rate DDR SDRAM
  51. There is always an 8:1 module-to-chip (or module to FSB speed) numbering ratio because of the 8 bytes that are transferred at a time with 64-bit processors ( not because of the ratio of 8 bits per byte). The following formula explains how this relationship works:
    • FSB in MHz (cycles/second) X 8 bytes (bytes/cycle) throughput (bytes/second)
    • Module Throughput Related to FSB Speed
  52. Think of the 2 in __ as yet another multiplier of 2 in the SDRAM technology, using a lower peak voltage to keep power consumption down (1.8V vs. the 2.5V of DDR). Still double-pumping, __, like DDR, uses both sweeps of the clock signal for data transfer. Internally, __ further splits each clock pulse in two, doubling the number of operations it can perform per FSB clock cycle. Through enhancements in the electrical interface and buffers, as well as through adding off-chip drivers, __ nominally produces four times the throughput that SDR is capable of producing.
  53. __ is a memory type that was designed to be twice as fast as the DDR2 memory that operates with the same system clock speed. Just as DDR2 was required to lower power consumption to make up for higher frequencies, __ must do the same. In fact, the peak voltage for __ is only 1.5V.The most commonly found range of actual clock speeds for DDR3 tends to be from 133MHz at the low end to less than 300MHz. Because double-pumping continues with __ and because four operations occur at each wave crest (eight operations per cycle), this frequency range translates to common FSB implementations from 1066MHz to more than 2000MHz in DDR3 systems. These memory devices are named following the conventions established earlier. Therefore, if you buy a motherboard with a 1600MHz FSB, you know immediately that you need a memory module populated with DDR3-1600 chips because the chips are always named for the FSB speed. Using the 8:1 module-to-chip/FSB naming rule, the modules you need would be called PC3-12800, supporting a 12800MBps throughput.
  54. __ named for Rambus, the company that designed it, is a legacy proprietary SDRAM technology, most often associated with server platforms. Although other specifications preceded it, the first motherboard __ model was known as PC800. As with non-DRDRAM specifications that use this naming convention, PC800 specifies that, using a faster 400MHz actual clock signal and double-pumping like DDR SDRAM, an effective frequency and FSB speed of 800MHz is created.
    Direct Rambus DRAM (DRDRAM)
  55. __ doesn't require a refresh signal like DRAM does. The chips are more complex and are thus more expensive. However, they are considerably faster. DRAM access times come in at 40 nanoseconds (ns) or more; __ has access times faster than 10ns. __is classically used for cache memory.
    Static random access memory SRAM
  56. __ is memory that cannot be written to. Once information had been etched on a silicon chip and manufactured into the __ package, the information couldn't be changed. If you ran out of use for the information or code on the __, you added little eyes and some cute fuzzy extras and you had a bug that sat on your desk and looked back at you. Some form of __ is normally used to store the computer's BIOS because this information normally does not change very often.
    read-only memory
  57. Through the years, different forms of ROM were developed that could be altered, later ones more easily than earlier ones. The first generation was the __, which could be written to for the first time in the field using a special programming device, but then no more.
  58. Following the PROM came __, which was able to be erased using ultraviolet light and subsequently reprogrammed using the original programming device. These days, our flash memory is a form of electronically __, which does not require UV light to erase its contents but rather a slightly higher than normal electrical pulse.
    Erasable PROM EPROM
  59. __ are 64-bit memory modules that are used as a package for the SDRAM family: SDR, DDR, DDR2, and DDR3. The term dual refers to the fact that, unlike their SIMM predecessors, __ differentiate the functionality of the pins on one side of the module from the corresponding pins on the other side. With 84 pins per side, this makes 168 independent pins on each standard SDR module. The __ used for DDR memory has a total of 184 pins and a single keying notch, while the __ used for DDR2 has a total of 240 pins, one keying notch, and possibly an aluminum cover for both sides, called a heat spreader and designed like a heat sink to dissipate heat away from the memory chips and prevent overheating. The DDR3 DIMM is similar to that of DDR2. It has 240 pins and a single keying notch, but the notch is in a different location to avoid cross insertion.
    dual inline memory module DIMM
  60. __ is a trademark of Rambus Inc. __is a custom memory module that carries DRDRAM and varies in physical specification, based on whether it is a 16-bit or 32-bit module. The 16-bit modules have 184 pins and two keying notches, while 32-bit modules have 232 pins and only one keying notch, reminiscent of the trend in SDRAM-to-DDR evolution. __ must always be installed in pairs, motherboards with the 16-bit single- or dual-channel implementation provide four RIMM slots that must be filled in pairs, while the 32-bit versions provide two RIMM slots that can be filled one at a time. A 32-bit RIMM essentially has two 16-bit modules built in (possibly contributing to the persistence of the belief in the “pair” requirement) and requires only a single motherboard slot, albeit a physically different slot. Unique to the use of __, a computer must have every __ slot occupied. Even one vacant slot will cause the computer not to boot. However, 32-bit modules terminate themselves and do not rely on the motherboard circuitry for termination, so vacant 32-bit slots require a module known as a continuity and termination __ (CT-RIMM).
    Rambus inline memory module RIMM
  61. __ are available in many physical implementations, including the older 32-bit (72- and 100-pin) configuration and newer 64-bit (144-pin SDR SDRAM, 200-pin DDR/DDR2, and 204-pin DDR3) configurations. All 64-bit modules have a single keying notch. The 144-pin modules notch is slightly off-center. Note that although the 200-pin __ for DDR and DDR2 have slightly different keying, its not so different that you dont need to pay close attention to differentiate the two. They are not, however, interchangeable.
    Small Outline DIMM
  62. The __ is an extremely small RAM form factor. In fact, it is over 50 percent smaller than a SODIMM, only 45.5 millimeters long and 30 millimeters wide. It was designed for the ultralight and portable subnotebook style of computer. Standard versions of these modules have 144 pins for SDR SDRAM, 172 pins for DDR DRAM, and 214 pins for DDR2 SDRAM. __ are similar to a DIMM in that they use a 64-bit data bus. The insertion keying of the __ for card-edge versions is reminiscent of the SIMM; only one notch and on one of the two insertion corners of the module instead of somewhere in the middle.
  63. __ takes advantage of the property of physics whereby reduction in voltage has an exponential effect on the reduction of power consumption and associated heat production. __ requires a BIOS (where the setting is made) and CPU combination that supports it. You should monitor the system for unpredictable adverse effects.